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1998 microchip technology inc. ds21132d-page 1 features single 5.0v supply low power cmos technology - 1 ma active current typical org pin selectable memory con?uration 1024 x 8- or 512 x 16-bit organization (93c76) 2048 x 8- or 1024 x 16-bit organization (93c86) self-timed erase and write cycles (including auto-erase) automatic eral before wral power on/off data protection circuitry industry standard 3-wire serial i/o device status signal during erase/write cycles sequential read function 1,000,000 erase/write cycles guaranteed data retention > 200 years 8-pin pdip/soic package temperature ranges supported description the microchip technology inc. 93c76/86 are 8k and 16k low voltage serial electrically erasable proms. the device memory is con?ured as x8 or x16 bits depending on the org pin setup. advanced cmos technology makes these devices ideal for low power non-volatile memory applications. these devices also have a program enable (pe) pin to allow the user to write protect the entire contents of the memory array. the 93c76/86 is available in standard 8-pin dip and 8- pin surface mount soic packages. - commercial (c): 0 c to +70 c - industrial (i): -40 c to +85 c - automotive (e) -40 c to +125 c package types block diagram soic package dip package cs clk di do v ss pe v cc org cs clk di do v cc pe org v ss 93c76/86 93c76/86 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 do cs clk v cc v ss memory array address decoder data register counter address output buffer mode decode logic generator clock di pe 93c76/86 8k/16k 5.0v microwire serial eeprom microwire is a registered trademark of national semiconductor incorporated.
93c76/86 ds21132d-page 2 1998 microchip technology inc. 1.0 electrical characteristics 1.1 maxim um ratings* v cc ...................................................................................7.0v all inputs and outputs w.r.t. v ss ............... -0.6v to vcc +1.0v storage temperature ..................................... -65?c to +150?c ambient temp. with power applied................. -65?c to +125?c soldering temperature of leads (10 seconds) ............. +300?c esd protection on all pins................................................4 kv *notice: stresses above those listed under ?aximum ratings may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability table 1-1: pin function table 1.2 a c t est conditions name function cs clk di do v ss org pe v cc chip select serial data clock serial data input serial data output ground memory con?uration program enable power supply ac waveform: v lo = 2.0v v hi = vcc - 0.2v (note 1) v hi = 4.0v for (note 2) timing measurement reference level input 0.5 v cc output 0.5 v cc note 1: for v cc 4.0v 2: for v cc > 4.0v table 1-2: dc characteristics applicable over recommended operating ranges shown below unless otherwise noted: v cc = +4.5v to +5.5v commercial (c): tamb = 0 c to -40 c industrial (i): tamb = -40 c to +85 c automotive (e): tamb = -40 c to +125 c parameter symbol min. max. units conditions high level input voltage v ih1 2.0 v cc +1 v low level input voltage v il1 -0.3 0.8 v low level output voltage v ol1 0.4 v i ol = 2.1 ma; v cc = 4.5v v ol2 0.2 v i ol =100 m a; v cc = 4.5v high level output voltage v oh1 2.4 v i oh = -400 m a; v cc = 4.5v v oh2 v cc -0.2 v i oh = -100 m a; v cc = 4.5v. input leakage current i li -10 10 m av in = 0.1v to v cc output leakage current i lo -10 10 m av out = 0.1v to v cc pin capacitance (all inputs/outputs) c int 7 pf (note) tamb = +25?c, f clk = 1 mhz operating current i cc write 3 ma f clk = 2 mhz; v cc = 5.5v i cc read 1.5 ma f clk = 2 mhz; v cc = 5.5v standby current i ccs 100 m a clk = cs = 0v; v cc = 5.5v di = pe = v ss org = v ss or v cc note: this parameter is periodically sampled and not 100% tested.
1998 microchip technology inc. ds21132d-page 3 93c76/86 table 1-3: ac characteristics applicable over recommended operating ranges shown below unless otherwise noted: v cc = +4.5v to +5.5v commercial (c): tamb = 0 c to -40 c industrial (i): tamb = -40 c to +85 c automotive (e): tamb = -40 c to +125 c parameter symbol min. max. units conditions clock frequency f clk 2 mhz vcc 3 4.5v clock high time t ckh 300 ns clock low time t ckl 200 ns chip select setup time t css 50 ns relative to clk chip select hold time t csh 0ns chip select low time t csl 250 ns relative to clk data input setup time t dis 100 ns relative to clk data input hold time t dih 100 ns relative to clk data output delay time t pd 400 ns c l = 100 pf data output disable time t cz 100 ns (note 1) status valid time t sv 500 ns c l = 100 pf program cycle time t wc 10 ms erase/write mode (note 2) t ec 15 ms eral mode t wl 30 ms wral mode endurance 1m cycles 25 c, v cc = 5.0v, block mode (note 3) note 1: this parameter is periodically sampled and not 100% tested. 2: typical program cycle is 4 ms per word. 3: this parameter is not tested but guaranteed by characterization. for endurance estimates in a speci? application, please consult the total endurance model which can be obtained on our website.
93c76/86 ds21132d-page 4 1998 microchip technology inc. table 1-4: instruction set for 93c76: org=1 (x16 organization) table 1-5: instruction set for 93c76: org=0 (x8 organization) table 1-6: instruction set for 93c86: org=1 (x16 organization) table 1-7: instruction set for 93c86: org=0 (x8 organization) instruction sb opcode address data in data out req. clk cycles read 1 10 x a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 29 ewen 1 00 1 1 x x x x x x x x high-z 13 erase 1 11 x a8 a7 a6 a5 a4 a3 a2 a1 a0 (rdy/bsy) 13 eral 1 00 1 0 x x x x x x x x (rdy/bsy) 13 write 1 01 x a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 (rdy/bsy) 29 wral 1 00 0 1 x x x x x x x x d15 - d0 (rdy/bsy) 29 ewds 1 00 0 0 x x x x x x x x high-z 13 instruction sb opcode address data in data out req. clk cycles read 1 10 x a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 22 ewen 1 00 1 1 x x x x x x x x x high-z 14 erase 1 11 x a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 (rdy/bsy) 14 eral 1 00 1 0 x x x x x x x x x (rdy/bsy) 14 write 1 01 x a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 (rdy/bsy) 22 wral 1 00 0 1 x x x x x x x x x d7 - d0 (rdy/bsy) 22 ewds 1 00 0 0 x x x x x x x x x high-z 14 instruction sb opcode address data in data out req. clk cycles read 1 10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 29 ewen 1 00 1 1 x x x x x x x x high-z 13 erase 1 11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 (rdy/bsy) 13 eral 1 00 1 0 x x x x x x x x (rdy/bsy) 13 write 1 01 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 (rdy/bsy) 29 wral 1 00 0 1 x x x x x x x x d15 - d0 (rdy/bsy) 29 ewds 1 00 0 0 x x x x x x x x high-z 13 instruction sb opcode address data in data out req. clk cycles read 1 10 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 22 ewen 1 00 1 1 x x x x x x x x x high-z 14 erase 1 11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 (rdy/bsy) 14 eral 1 00 1 0 x x x x x x x x x (rdy/bsy) 14 write 1 01 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 (rdy/bsy) 22 wral 1 00 0 1 x x x x x x x x x d7 - d0 (rdy/bsy) 22 ewds 1 00 0 0 x x x x x x x x x high-z 14
1998 microchip technology inc. ds21132d-page 5 93c76/86 2.0 principles of operation when the org pin is connected to v cc , the x16 orga- nization is selected. when it is connected to ground, the x8 organization is selected. instructions, addresses and write data are clocked into the di pin on the rising edge of the clock (clk). the do pin is normally held in a high-z state except when reading data from the device, or when checking the ready/b usy status dur- ing a programming operation. the ready/b usy sta- tus can be veri?d during an erase/write operation by polling the do pin; do low indicates that programming is still in progress, while do high indicates the device is ready. the do will enter the high impedance state on the falling edge of the cs. 2.1 st ar t condition the start bit is detected by the device if cs and di are both high with respect to the positive edge of clk for the ?st time. before a start condition is detected, cs, clk, and di may change in any combination (except to that of a start condition), without resulting in any device oper- ation (read, write, erase, ewen, ewds, eral, and wral). as soon as cs is high, the device is no longer in the standby mode. an instruction following a start condition will only be executed if the required amount of opcode, address and data bits for any particular instruction are clocked in. after execution of an instruction (i.e., clock in or out of the last required address or data bit) clk and di become don't care bits until a new start condition is detected. 2.2 di/do it is possible to connect the data in and data out pins together. however, with this con?uration it is possible for a ?us con?ct to occur during the ?ummy zero that precedes the read operation, if a0 is a logic high level. under such a condition the voltage level seen at data out is unde?ed and will depend upon the relative impedances of data out and the signal source driving a0. the higher the current sourcing capability of a0, the higher the voltage at the data out pin. 2.3 erase/write enab le and disab le (ewen, ewds) the 93c76/86 powers up in the erase/write disable (ewds) state. all programming modes must be pre- ceded by an erase/write enable (ewen) instruction. once the ewen instruction is executed, programming remains enabled until an ewds instruction is executed or v cc is removed from the device. to protect against accidental data disturb, the ewds instruction can be used to disable all erase/write functions and should follow all programming operations. execution of a read instruction is independent of both the ewen and ewds instructions. 2.4 data pr otection during power-up, all programming modes of operation are inhibited until v cc has reached a level greater than 1.4v. during power-down, the source data protection circuitry acts to inhibit all programming modes when v cc has fallen below 1.4v. the ewen and ewds commands give additional pro- tection against accidentally programming during nor- mal operation. after power-up, the device is automatically in the ewds mode. therefore, an ewen instruction must be performed before any erase or write instruction can be executed.
93c76/86 ds21132d-page 6 1998 microchip technology inc. 3.0 device operation 3.1 read the read instruction outputs the serial data of the addressed memory location on the do pin. a dummy zero bit precedes the 16 bit (x16 organization) or 8 bit (x8 organization) output string. the output data bits will toggle on the rising edge of the clk and are stable after the speci?d time delay (t pd ). sequential read is possible when cs is held high and clock transitions continue. the memory address pointer will automati- cally increment and output data sequentially. 3.2 erase the erase instruction forces all data bits of the spec- i?d address to the logical ? state. the self-timed pro- gramming cycle is initiated on the rising edge of clk as the last address bit (a0) is clocked in. at this point, the clk, cs, and di inputs become don? cares. the do pin indicates the ready/b usy status of the device if the cs is high. the ready/b usy status will be displayed on the do pin until the next start bit is received as long as cs is high. bringing the cs low will place the device in standby mode and cause the do pin to enter the high impedance state. do at logical ? indicates that programming is still in progress. do at logical ? indicates that the register at the speci?d address has been erased and the device is ready for another instruction. the erase cycle takes 3 ms per word (typical). 3.3 write the write instruction is followed by 16 bits (or by 8 bits) of data to be written into the speci?d address. the self-timed programming cycle is initiated on the ris- ing edge of clk as the last data bit (d0) is clocked in. at this point, the clk, cs, and di inputs become don? cares. the do pin indicates the ready/b usy status of the device if the cs is high. the ready/b usy status will be displayed on the do pin until the next start bit is received as long as cs is high. bringing the cs low will place the device in standby mode and cause the do pin to enter the high impedance state. do at logical ? indicates that programming is still in progress. do at logical ? indicates that the register at the speci?d address has been written and the device is ready for another instruction. the write cycle takes 3 ms per word (typical). 3.4 erase all (eral) the eral instruction will erase the entire memory array to the logical ? state. the eral cycle is identical to the erase cycle except for the different opcode. the eral cycle is completely self-timed and com- mences on the rising edge of the last address bit (a0). note that the least signi?ant 8 or 9 address bits are don? care bits, depending on selection of x16 or x8 mode. clocking of the clk pin is not necessary after the device has entered the self clocking mode. the eral instruction is guaranteed at vcc = +4.5v to +5.5v. the do pin indicates the ready/b usy status of the device if the cs is high. the ready/b usy status will be displayed on the do pin until the next start bit is received as long as cs is high. bringing the cs low will place the device in standby mode and cause the do pin to enter the high impedance state. do at logical ? indicates that programming is still in progress. do at logical ? indicates that the entire device has been erased and is ready for another instruction. the eral cycle takes 15 ms maximum (8 ms typical). 3.5 write all (wral) the wral instruction will write the entire memory array with the data speci?d in the command. the wral cycle is completely self-timed and commences on the rising edge of the last address bit (a0). note that the least signi?ant 8 or 9 address bits are don? cares, depending on selection of x16 or x8 mode. clocking of the clk pin is not necessary after the device has entered the self clocking mode. the wral command does include an automatic eral cycle for the device. therefore, the wral instruction does not require an eral instruction but the chip must be in the ewen sta- tus. the wral instruction is guaranteed at vcc = +4.5v to +5.5v. the do pin indicates the ready/b usy status of the device if the cs is high. the ready/b usy status will be displayed on the do pin until the next start bit is received as long as cs is high. bringing the cs low will place the device in standby mode and cause the do pin to enter the high impedance state. do at logical ? indicates that programming is still in progress. do at logical ? indicates that the entire device has been written and is ready for another instruction. the wral cycle takes 30 ms maximum (16 ms typi- cal).
1998 microchip technology inc. ds21132d-page 7 93c76/86 figure 3-1: synchronous data timing figure 3-2: read figure 3-3: ewen figure 3-4: ewds the memory automatically cycles to the next register. v ih v il v ih v il v ih v oh v ol v oh v ol v il t sv t dis t pd t dih t css t ckh t ckl t pd t csh t cz t cz cs clk di do do (program) (read) status valid 110a n a 0 d n d n d 0 d 0 ... ... ... high impedance t csl cs clk di do 0 ewen cs clk di 111 00 t csl xx ... org=v cc , 8 xs org=v ss , 9 xs 10000x x ... cs clk di t csl org=v cc , 8 xs org=v ss , 9 x?
93c76/86 ds21132d-page 8 1998 microchip technology inc. figure 3-5: write figure 3-6: wral figure 3-7: erase 101a n a 0 ... d n ... d 0 t wc ready b usy high impedance cs clk di do standby t cz guarantee at vcc = +4.5v to +5.5v. 10001x ... xd n ... d 0 b usy ready high impedance standby cs clk di do org=v cc , 8 xs org=v ss , 9 xs t wl t cz 11 1a n ... a 0 t cz high impedance cs clk di do standby ready b usy t wc ...
1998 microchip technology inc. ds21132d-page 9 93c76/86 figure 3-8: eral guarantee at v cc = +4.5v to +5.5v. org=v cc , 8 xs org=v ss , 9 xs 10 010x x ... cs clk di do t ec t cz high impedance b usy ready standby 4.0 pin descriptions 4.1 chip select (cs) a high level selects the device. a low level deselects the device and forces it into standby mode. however, a programming cycle which is already initiated will be completed, regardless of the cs input signal. if cs is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. cs must be low for 250 ns minimum (t csl ) between consecutive instructions. if cs is low, the internal control logic is held in a reset status. 4.2 serial cloc k (clk) the serial clock is used to synchronize the communi- cation between a master device and the 93c76/86. opcode, address, and data bits are clocked in on the positive edge of clk. data bits are also clocked out on the positive edge of clk. clk can be stopped anywhere in the transmission sequence (at high or low level) and can be contin- ued anytime with respect to clock high time (t ckh ) and clock low time (t ckl ). this gives the controlling master freedom in preparing opcode, address, and data. clk is a ?on't care if cs is low (device deselected). if cs is high, but start condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for start condition). clk cycles are not required during the self-timed write (i.e., auto erase/write) cycle. after detection of a start condition the speci?d number of clock cycles (respectively low to high transitions of clk) must be provided. these clock cycles are required to clock in all opcode, address, and data bits before an instruction is executed (see table 1-4 through table 1-7 for more details). clk and di then become don't care inputs waiting for a new start condi- tion to be detected. 4.3 data in (di) data in is used to clock in a start bit, opcode, address, and data synchronously with the clk input. 4.4 data out (do) data out is used in the read mode to output data syn- chronously with the clk input (t pd after the positive edge of clk). this pin also provides ready/b usy status informa- tion during erase and write cycles. ready/b usy status information is available when cs is high. it will be displayed until the next start bit occurs as long as cs stays high. 4.5 or ganization (org) when org is connected to v cc , the x16 memory orga- nization is selected. when org is tied to v ss , the x8 memory organization is selected. there is an internal pull-up resistor on the org pin that will select x16 organization when left unconnected. 4.6 pr ogram enab le (pe) this pin allows the user to enable or disable the ability to write data to the memory array. if the pe pin is ?ated or tied to v cc , the device can be programmed. if the pe pin is tied to v ss , programming will be inhib- ited. there is an internal pull-up on this device that enables programming if this pin is left ?ating. note: cs must go low between consecutive instructions, except when performing a sequential read (refer to section 3.1 for more detail on sequential reads).
93c76/86 ds21132d-page 10 1998 microchip technology inc. notes:
93c76/86 93c76/86 pr oduct identi cation system to order or obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or t he listed sales of?e. sales and suppor t data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales of?e 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip worldwide web site (www.microchip.com) 93c76/86 \p package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead temperature blank = 0 c to +70 c range: i = -40 c to +85 c e = -40 c to +125 c device: 93c76/86 microwire serial eeprom 93c76t/86t microwire serial eeprom (tape and reel) 1998 microchip technology inc. ds21132d-page 11
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8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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